Serial 2 S Complementer Shift Register

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1 Answer to Design a 2's complementer with a shift register and a flip-flop. The binary # is shifted out from one side and it's 2's complement shifted into the. Answer to design a serial 2's complementer with a shift register and a flip flop. The binary number is shifted out from one side a.

Serial 2 S Complementer Shift Register

Complaints About Epicor Software. I apologize for the ambiguity of my post. # of bits all depends on the input SYNC. When SYNC is high, this means a new number is starting. The LSB is entered first through the DATA input. So for example: SYNC: 1 0 0 0 0 0 1 0 0 0 0 0 0 0. DATA: 1 0 0 1 1 1 0 0 0 1 1 0 1 0. Output: 1 1 1 0 0 0 0 0 0 1 0 1 0 1.

The inputs are entered one at a time, not all at once. There is also a clock attached to this. It should be relatively easy, but I'm just not getting Mealy machines. Oh and, we have to use D or JK flip-flops. So now we have a new problem. It would seem that this machine is required to predict the final result before all the bits have been received.

I'm going to out on a limb and say I think that this assignment defined the way you have defined it is quite plainly impossible. This is not about Mealy machines it is about a set of requirements and specifications that make sense. There are many other problems with this specification but lets concentrate on precognition and the length of a maximum sequence. It comes back to the realm of possibility if the output can be delayed until the next sysnc pulse so you know how long the data is. This is why we used ones complement Arithmetic in the serial arithmetic logic units that we designed with TTL parts in the early 1970's.

The complementer is a simple combinatorial circuit, no memory required, and a ones complement ALU only needs an end around carry to complete the process. Click to expand.Saying it is 'quite plainly impossible' only signifies a lack of understanding of the problem. This is most definitely a solvable problem, and quite easily doable with both Mealy and Moore FSMs. Without giving away the 'answer' (so as not to provide a cheat for EE students that have this or a similar problem to solve in their class), I will just give the following hint: Use the short-cut method to finding 2's complement on a serial bitstream.

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